Analog and low pin count device test cells may often use ‘turret’ style handlers, in which each stage can be configured to do a specific back-end process task in a serial manner.
Due to this serial, single flow “production line” design, a turret handler approach adds inefficiencies. The whole process only goes as fast as the slowest stage. The overall UPH decreases significantly as test time increases. The classical multisite test is non-ideal and adds a significant overhead to the process flow.
If devices are designed appropriately and a suitable ATE architecture is used, functional blocks of a test program can be distributed amongst multiple stages and reduce the test duration per stage, which increases throughput and reduces cost of test. In the best case, test time can be fully masked and will consume zero process time. The presentation describes required features of an ATE architecture that support such a “Distributed Test” approach and the COT benefits that can be realised.