There are major trends for reduced form factors and increased functionality of ICs as well as enhanced requirements regarding electrical performance and power dissipation. These trends drive TSV packaging and 3D IC solutions. Stacking dies bears a much higher risk for failure than single die technologies: failures may happen in the dies themselves, but additionally in the interposers, in the laminations and in the connections. Bad parts in the stack will corrupt good ones. The worst scenario adds a cost-intensive component such as the a memory on a stack, which is dysfunctional. The KGD concept only partly can solve this. Advanced packaging processes not only require total reliability of the overall supply chain but also require advanced models to reduce the risk of unprofitable output caused by the packaging process itself.
In traditional semiconductor production, component test (for KGD) and final test for ultimate functional QA before shipment are sufficient to ensure quality but also cost-efficiency. Advanced packing methods such as 3D go beyond this. This paper will discuss ways for a distributed test flow which compare the cost of test with the cost of non-testing with special references to the packaging process. It will also highlight the opportunities and challenges of distributed test strategies and analyze the best models for this test distributions and the special equipment requirements.