Power integrity is the discipline of providing clean power to the DUT by minimizing noise on the Power Delivery Network (PDN). It is quickly becoming one of the biggest challenges in test interface design. By maintaining a low impedance path from tester to DUT across all operating frequencies of the device, a constant voltage can be provided to the DUT in high di/dt environment.
After providing an overview of power integrity, this presentation describes how power integrity relates specifically to the test interface, beginning with the load board. When comparing the load board to a typical final application board, the load board has significant differences due its size. In PDN design, there are many tradeoffs that need to be understood, and the thickness and size of the load board needs to be considered.
Next, the presentation will describe the impact of the contactor. The contactor can have a significant impact on the ability of the PDN to provide clean power to the DUT. It is important to understand the contactor’s influence on the PDN. This presentation will discuss the variables that impact how and when the contactor impacts the PDN.
Power integrity is a challenge whose influence will continue to increase in the coming years. It is becoming increasingly important for the test community to understand the issues and improve their ability to address the power integrity challenges that are caused by the test interface.