This presentation explains the benefits and risks of high-aspect-ratio though-hole vias in high-density and fine-pitch printed circuit boards used in the test interface. Users are facing challenges as I/O counts increase, circuitry requirements have added to ATE PCB density, and array packages shrink below 0.65 mm pitch.
This is leading some users to incorporate laser drilled micro vias & multi-book sequential laminations to accomplish interconnect. By using high-aspect-ratio vias in conjunction with reduced trace widths, fine-pitch & high-density designs can be simplified with the added benefit of reducing layer counts and, consequently, costs.
Two examples are shared: 1. How design for manufacturability rules using high aspect ratio vias reduced layer count and overall thickness in a ultra-high-density wafer-level test board design. 2. How these same PCB construction methods were used to eliminate the need for micro via/multi book sequential lamination in a 0.5 mm pitch WLCSP interface.
Positive and negative aspects of the two construction methods are examined, including cost factors (why some features cost more than others) and lead-time implications, a basic overview of signal integrity impacts of the geometries involved, and a breakdown of PCB construction methods, including the limitations of both laser drilling micro vias and mechanically-drilled high-aspect-ratio vias.